vhdl - How to take samples using fpga? -

i want take samples of digital data coming externaly fpga spartan 3. want take 1000 samples/sec initially. how select clock frequency in vhdl coding?

thanks.

do not use counter generate lower frequency clock signal.

multiple clock frequencies in fpga cause variety of design problems, of come under heading of "advanced topics" and, while can (if necessary) dealt , solved, learning how use single fast clock both simpler , better practice (synchronous design).

instead, use whatever fast clock fpga board provides, , generate lower frequency timing signals it, , - crucially - use them clock enables, not clock signals.

dlls, dcms, plls , other clock managers have uses, generating 1 khz clock signals not use, if limitations permit it. application crying out clock enable...

also, don't mess around magic numbers, let vhdl compiler work! have put timing requirements in package, can share them testbench , else needs use them.

package timing      -- change first 2 constants match system requirements...     constant clock_freq  : real := 40.0e6;     constant sample_rate : real := 1000.0;      -- these calculated above, stay correct when make changes     constant divide      : natural := natural(clock_freq / sample_rate);     -- need period, e.g. in testbench.     constant clock_period : time := 1 sec / clock_freq;  end package timing; 

and can write sampler follows: (i have split clock enable out separate process clarify use of clock enables, 2 processes rolled 1 further simplification; "sample" signal unnecessary)

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.timing.all;  entity sampler     port (         clock   : in  std_logic;         reset   : in  std_logic;         adc_in  : in  signed(7 downto 0);            -- signed audio, or unsigned, depending on app         sampled : out signed(7 downto 0);        ); end sampler;  architecture behavioral of sampler     signal sample : std_logic; begin      gen_sample : process (clock,reset)      variable count : natural;     begin         if reset = '1'             sample     <= '0';             count      := 0;         elsif rising_edge(clock)             sample     <= '0';             count      := count + 1;             if count = divide                 sample <= '1';                 count  := 0;             end if;         end if;     end process;      sample_data : process (clock)      begin         if rising_edge(clock)             if sample = '1'                 sampled <= adc_in;             end if;         end if;     end process;  end behavioral;