gnu make - how Makefiles work exactly -
i'm writing code gtk application written in c, , have questions it.
# compiler cc = gcc cflags = -wall -g -o rm = rm -f # additional header path gtkinc = `pkg-config --cflags gtk+-3.0` gtklib = `pkg-config --libs gtk+-3.0` inc = $(gtkinc) liblnk = $(gtklib) # sources, objects, executable srcs = hello.c objs = $(srcs:.c = .o) exec = hello .phony: clean all: $(exec) @echo compile complete $(exec): $(objs) $(cc) $(inc) $(cflags) $(exec) $(objs) $(liblnk) clean: $(rm) *.o *~ $(exec) previously, when wrote makefiles,i added lines each object files
for example
blah blah a.o: 1.h a.c b.c $(cc) blah blah blah blah and then, got little lazy , tried make more easy-to-modify file googling up, , product above code. 1. same thing did previously?(like in example) found out code compiles properly, i'm not sure if checks out-of-date object files.(which whole meaning of 'make')
2. have to use 'depend' on header files in order check out-of-date source files?? 3. it's bit out of subject, what's difference between gcc -o hello.o hello.h hello.c , gcc -c hello.c ?
2.have use 'depend' on header files in order check out-of-date source files
you should auto-generate dependencies on header files. see https://stackoverflow.com/a/9598716/412080
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