assembly - List of Hidden ARM 3 Letter mnemonics -

x86 has had cases of manufacturer inserting, new, undocumented opcodes @ time. due arm holdings lack of fab plant, there 'hidden' opcodes inserted licentiate. after using google-fu theory seems incorrect. documentation, or past experiences -- know of 'hidden mnemonics'?

xscale can visible example of such fork. intel @ time added own instructions provide more media capable core.

from intel xscale® core developer’s manual:

2.3 extensions arm architecture

3rd generation microarchitecture extends armv5te architecture meet needs of various markets , design requirements. following list of extensions discussed in subsequent sections.

• a media processing co-processor (cp0) has been added contains 40-bit internal accumulator. 5 new instructions have been added access 40- bit accumulator. page attributes added page table descriptors , description of existing attributes in armv5te enhanced. note compatibility maintained software developed using page table attributes previous microarchitectures.
• co-processor 7 , co-processor 14 registers added 3rd generation microarchitecture.
• co-processor 15 functionality extended , new registers added.
• enhancements made exception architecture, include instruction cache , data cache parity error exceptions, debug exceptions, , imprecise external data aborts.

qualcomm @ writing time of post intel more closed approach. may don't directly add new instructions cores try modify them in way give them advantage on other arm cores. example simd instructions, qualcomm has own co-processor called venum , has less limitations of register addressing compared arm cores - read michael's comment example.