compiler errors - Signal is connected to following multiple drivers -

i trying run following , receive error:

here's verilog code:

module needle( input referrence,input  penalty,output index[7:0]); //inout input_itemsets; //input referrence;  //input penalty; //output index; parameter max_cols=8; // wire index[7:0]; wire referrence; wire penalty; //wire input_itemsets; genvar i,idx; generate for( = max_cols-4 ; >= 0 ; i=i-1)     for( idx = 0 ; idx <= ; idx=idx+1)         begin              assign index[i] = (idx + 1) * max_cols + (i + 1 - idx);              //assign index = (idx + 1) * max_cols + (i + 1 - idx);             //input_itemsets[index] <= maximum( input_itemsets[index-1-max_cols]+ referrence[index],             //input_itemsets[index-1] - penalty,             //input_itemsets[index-max_cols] - penalty);          end    endgenerate  endmodule 

and here's warnings , errors receive:

warning:hdlcompiler:413 - "/home/suriyha/monajalal/needle_t1/needle.v" line 39: result of 4-bit expression truncated fit in 1-bit target. error:hdlcompiler:1401 - "/home/suriyha/monajalal/needle_t1/needle.v" line 39: signal  index[3] in unit needle connected following multiple drivers: driver 0: output signal of instance power (pwr_1_o_buf_9). driver 1: output signal of instance ground (gnd_1_o_buf_8). driver 2: output signal of instance ground (gnd_1_o_buf_6). driver 3: output signal of instance ground (gnd_1_o_buf_4). driver 4: output signal of instance ground (gnd_1_o_buf_11). module needle remains blackbox, due errors in contents warning:hdlcompiler:1499 - "/home/suriyha/monajalal/needle_t1/needle.v" line 21: empty module <needle> remains black box. 

however main code "assign index = (idx + 1) * max_cols + (i + 1 - idx);" decided make "index" array avoid problem, yet running it. no matter if index array or variable yet have multiple value problem.

also c version of code :

for( idx = 0 ; idx <= ; idx++){     index = (idx + 1) * max_cols + (i + 1 - idx);     input_itemsets[index]= maximum( input_itemsets[index-1-max_cols]+ referrence[index],     input_itemsets[index-1] - penalty,      input_itemsets[index-max_cols] - penalty);  } 

i know if can have nested loop have in c counter part in verilog version or how avoid "multiple driver" problem in case??

thanks.

in verilog code, index bits constants either double driven(x) or not driven(z): index[7:0]:zzzxxxx1

the explanation following. outer loop 4 0, means index[7:5] undriven(z). inner loop 0 i, unrolls following:

assign index[4] = (0 + 1) * max_cols + (4 + 1 - 0); assign index[4] = (1 + 1) * max_cols + (4 + 1 - 1); ... assign index[1] = (0 + 1) * max_cols + (1 + 1 - 0); assign index[1] = (1 + 1) * max_cols + (1 + 1 - 1); assign index[0] = (0 + 1) * max_cols + (0 + 1 - 0); 

so index[4:1] double driven(x), , index[0] has single driver.

compiled code test here: eda playground