verilog - What division algorithm should be used for dividing small integers in hardware? -

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i need multiply integer ranging 0-1023 1023 , divide result number ranging 1-1023 in hardware (verilog/fpga implementation). multiplication straight forward since can away shifting 10 bits (and if needed i'll subtract 1023). division little interesting though. area/power arent't critical me (i'm in fpga resources there). latency (within reason) isn't big deal long can pipeline deisgn. there several choices different trade offs, i'm wondering if there's "obvious" or "no brainer" algorithm situation this. given limited range of operands , abundance of resources have (bram etc) i'm wondering if there isn't obvious do.

if can work fixed point precision rather integers may possible change :

divide result number ranging 1-1023

to multiplication number ranging 1 - 1/1023, ie pre-compute divide , store coefficient multiply.


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